Low-Power Circuit Techniques for Low-Voltage Pipelined ADCs Based on Switched-Opamp Architecture

This paper proposes useful circuit structures for achieving a low-voltage/low-power pipelined ADC based on switched-opamp architecture. First, a novel unity-feedback-factor sample-and-hold which manipulates the features of switched-opamp technique is presented. Second, opamp-sharing is merged into switched-opamp structure with a proposed dual-output opamp configuration. A 0.8-V, 9-bit, 10-Msample/s pipelined ADC is designed to verify the proposed circuit. Simulation results using a 0.18-μm CMOS 1P6M process demonstrate the figure-of-merit of this pipelined ADC is only 0.71 pJ/step. key words: low-voltage, switched-opamp, sample-and-hold, opampsharing, pipelined ADC